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AD9914 PLL input divider and multiplier questions

Question asked by KE5FX on Dec 21, 2013
Latest reply on Dec 21, 2013 by KE5FX

Hi -- I'm working with the AD9914 eval board and ran into a couple of questions. 


First, I see in the data sheet (rev C, page 41) that CFR3[16], Doubler clock edge, "enables the doubler circuit," and "must have doubler enable bit set to Logic 1 to utilize this feature."  Likewise, the description for CFR3[19], Doubler enable, says, "Must have the doubler clock edge bit set to Logic 1 to utilize this feature."  In other words, each bit description says that the other bit needs to be set to '1'.  So my initial takeaway was that, in order to use the clock doubler, I needed to set both CFR3[16] and CFR3[19] to 1. 


However, I've noticed that when using the doubler, the phase noise floor seems 1 to 3 dB better when setting CFR3[19] to 0:


Any word on the correct usage of these bits?  Is this difference in the PN floor likely to be consistent?  It seems to work OK either way but for some reason the signal seems a bit cleaner with CFR3[16]=0, at least at this particular output frequency. 


Question #2: I can't seem to get the input divider feature (CFR3[21:20]) to do anything at all, either in my own software or in the (rather clunky) AD9914 evaluation app.  Is there a particular sequence of operations I can use in the demo app to verify that the input divider works on my eval board?  I can program the Input divider bits (CFR3[21:20]) and read them back with no problem, they just don't have any effect.  The input division ratio is always effectively 1.  Do I need to do anything special with CFR3[22], Input divider reset, to get the input divider to work?  Also, how do the available input division factors (1,2,4,8) map to the CFR3[21:20] bits?  This doesn't seem to be documented anywhere.


Thanks for any hints.