AnsweredAssumed Answered

Link Port 21469, LCLK0 stay high

Question asked by corleone on Dec 19, 2013
Latest reply on Jan 21, 2014 by Jithul_Janardhanan



i try to get the 16 bit parallel from the ad7606 into the dsp.

with the DAI Pins i can control the adc ad 7606.

My plan was to use the both 8 bit link port as reciever to read the data from the adc, but

the adc send his data only when it get an clock signal. This signal i generate with my

program. This clock signal is also connect to the LCLK0 and LCLK1 of the eval board.


"Self made" Clock signal go to:


                    -> LCLK1

                    -> CS, RD of AD7606



ad7606 DB 0-15 -> LDATA0_0 - LDATA0_7 and LDATA1_0 - LDATA1_7


Porblem is, that the LCLK0 stay high, after i enable this port with:


*pLCTL0 = *pLCTL1 = 0;

*pLCTL0 = (LEN | LP_BHD);

*pLCTL1 = (LEN | LP_BHD);


befor this part of the programm both, LCLK0 and LCLK1, are LOW

after this code, the LCLK1 stay LOW, but the LCLK0 go HIGH.


The result is that my generated clock signal go only between 1.6 and 3.3V, so i have no LOW part.

When i disable the link port 0, the signal have clean edges between 0 and 3.3V, i can read 8bit of the 16bit from the adc, but i need both ports.


Im don't know why this happen, maybe there is another register where i have to set something, or

the dsp allows only one reciever of the link ports, or i have to use a specific position of the switches wich are on the eval board, or this thing is simply broken.


Does somebody use both link ports as reciever without DMA? or have an idea why this is happen?