Can you offer the standard register setting file of ADV7513.
The ADV7513 is similar to the ADV7511 except for package and output bus width. In the attached script the writes to address 72 are the ADV7511 writes. Make sure your input format and bus rotation matches your design and select the appropriate script to match your resolution and you should be fine.
I have several questions.
1、What kind of function is HPD（hot plug detection）?
Our system is connected to the monitor through a DVI cable.
I let you output a picture of 1920x1080 60i.
I do not use the HDCP function.
2、When I do not use HDCP function, should I be connected to the voltage more than 1.2V?
3、What kind of case do you use Pull Down in 10kΩ at the time of?
I was pull down 16pin in 10kΩ
Then malfunction occurred.（Register setting is not load.）
After connecting a power supply of 5V to 16pin, it was largely improved.
1) HPD is a signal from the sink to the source that indicates the monitor is connected. Normally it is tied to +5V at the sink. Normally the 7513 will not transmit until it sees a valid HPD signal (high) and detects the proper termination on the TMDS clock line. You can override these checks via software.
2) It's best to pull HPD tie high if the source isn't going to use it
3) Normally the source will pull HPD high through a ~1k resistor. the 10K on the transmitter side of the cable is just to keep it pulled down in case the sink is disconnected
1.P36.（HARDWARE USER’S GUIDE REV.0）
「（6.6.1 Two-Wire Serial Control Port）…The user should wait 200ms for the address to be decided, after the power supplies are high, before attempting to communicate with the ADV7511W using I2C」
⇒Is ADV7511W of the sentence ADV7513?
2.Can you change a register during operation?
1) ADV7511, ADV7511W and ADV7513 are basically the same part.
2) If you mean I2C registers then no, let the 200 ms expire before doing any writes. Also the address select should be stable for those 200ms
I am having trouble now about ADV7513.
Because output clock Jitter of ADV7513 is big.
I measured ADV7513 and AD9889B.
AD9889B 150ps ：no problem
ADV7513 350ps ：There is a problem.
（condition: DVI, 1,980*1,080 60Hz）
Measuring method for jitter.
Wave pattern quality of input Clock
PCB artwork of the output is the same.
The power supply to an IC satisfies precision of ADV7513.
If there are the contents which I should confirm other than these, please tell me.
(Setting of the register in conjunction with Jitter...etc)
About a rule of the jitter of input clock of ADV7513.
It is listed in AD9889B with CLK Input Jitter (Max 2ns).
Please tell me the Max level of ADV7513.
(The signal is used in 74.25MHz)
About a mention of AD9889B-to-ADV7513-Changeover-Guide
「Improved PLL for elimination of frequency ‘gear’ hopping in automatic mode.」
Please tell me about contents for change.
Do you influence the Clock output of ADV7513?
Are you measuring the jitter on one of our reference boards?
Jitter is has several possible sources.
a) PVDD power and PLL filter has to be very clean
b) noise injected by other circuits
1) The evaluation board meets HDMI compliance of which jitter is one of the tests.
2) The AD9889B is an old and jitter was spec'd per HDMI 1.2 in nanoseconds. The ADV7513 is newer and was spec'd per HDMI1.4 in UIs which is resolution independent.
3) The gear hopping just refers to better PLL response as formats are changed
Thank you for your reply.
1.Please tell me the quantity of clock jitter(ps) when I measured on a compliance test.
2.Please tell me the machine parts which you used for a measurement.
1.Is my understanding correct about a rule of the clock jitter?
→ADV7513 is 1920x1080i 60Hz when it is 1.88ns(＝1.4UI＝1.4ｘ1.347ns).
1.Does The gear hopping always fluctuate? or
2.When you changed format, will you perform it only once?
1) 1. According to HDMI CTS version 1 Test ID 7-9: TMDS clock jitter for 720p60 = 3.37ns
1) 2. The testing was done in an authorized test center using equipement specified or allowed by the CTS
2) 1. clock jitter @ 1080i30 -> 74.25MHz clock -> 0.25UI -> 3.37ns if I did the math correct.
3) 1. gear hopping should occur when the input format changes, There may be slight various ( almost unnoticable ) in the PLL to keep up with the active input but it should be relatively stable.
I want to confirm it about CLK Input Jitter.
Data sheet of AD9889B of the HDMI1.2 conformity wrote it as maximum 2ns.
Please tell me the maximum of ADV7513 of the HDMI1.4 conformity.
The ADV7513 input pixel bus timing is defined in the hardware guide Figure 2. No input clock jitter is defined or needed as long as you meet the input timing constraints.
The output clock jitter meets HDMI 1.4 compliance.
Please tell me the maximum of 'Worst Case CLK Input Jitter' of ADV7513.
The ADV7513 input pixel clock is an input, it does not generate jitter. Any input clock jitter is caused by the source driving the input. As long as you meet the input timing requirements the input pixel port will work.
The output TMDS clock jitter meets HDMI 1.4 specifications which is defined in Tbit values. I do not have hard nanosecond numbers for the jitter. If you truly need a number you can extract it from the specification at the highest resolution the device will support.
Exactly what is driving this question. What in your implementation requires hard, specific jitter values in nanosecond numbers? We might be having translation issues, maybe I don't understand the question completely. Can you contact your local ADI FAE, he might be able to help here.
Thank you for your support in your busy time.
Please tell me the concrete numeric value in input pixel clock jitter.
In this case,The max resolution of input data rate is 165MHz(1080p @ 60Hz, UXGA @ 60Hz)
The input clock does not have an input clock jitter specification. As long as you meet the timing requirements you should be fine.
When the HPD pin is 1, is there any signals or resisters changed by Power down pin polarity (active-High or active-Low) ?
if We use I2C address = 0x7A, output Clock jitter is small,
but use I2C address =0x72, output Clock jitter is bigger.
we use 2 ADV7513, then Read Data are Following:
What should we do for decrease the Output Clock jitter?
Please reply to me.
The ADV7513 is a HDMI transmitter. The only output clock is the TMDS clock on the HDMI output. Using different addresses should not cause jitter problems. Nor different polistry on the power down pin. The only difference could be in the power supply or grounding issues.
Why are you using different power down polarity for two of the same chips on the same board?
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