I'm using the 2013R1-RC1 buildroot release, the only change from bf537-stamp_defconfig was to enable the bfin_sport module.
I need to read 8 channels in TDM mode from the CS5368 8-channel ADC in at 48kHz sample rate.
The CS5368 will be in master mode, this means 3 outputs from the CS5368 connected to SPORT0 inputs (clock, frame sync, data).
Each frame consists of 8 channels, 32 bits each (24 of which are valid, and I need just the 16 MSBs).
Right now, the ADC is not connected yet (waiting for the CDB5368 eval board to arrive), so I expect any TDM read operation to hang waiting for the necessary number of clock edges. But, right after open() and config ioctl(), the first read() already results in "Unbalanced enable for IRQ" warnings followed by lots of other kernel messages. Is this a known bug, or am I doing something wrong? Simple application source (doing just a single read) to show the issue is attached.
Another question - the intended use is to stream all samples over the network in UDP packets. Can I expect the bfin_sport driver in DMA mode to perform well enough to handle continuous read (no lost samples) of 8 channels at 48kHz sample rate?