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ADV7181D 12 bit RGB 4:4:4 DDR mode

Question asked by jerivera on Dec 12, 2013
Latest reply on Dec 20, 2013 by GuenterL

On this mode, half of the data is sent on the rising edge of the LLC clock, and the other half is on the falling edge. Assuming the video source is 525i RGB with SOG (SD) the LLC clock is 27Mhz, or 2X the pixel rate. Does this mean that every RGB 12 bit set is repeated twice, the data being alternated on rising and falling edges? Can someone provide a timing diagram of this mode?


Jose Rivera

Lockheed Martin Orlando Fl