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ADIS16485 no data output, also no current consumption

Question asked by Mikkie on Dec 12, 2013
Latest reply on Dec 13, 2013 by NevadaMark

Just received an ADIS16485 but are having some trouble to get data out.

 

I am interfacing to the ADIS with an FPGA. My ADIS nRST is tristated

There is 3V3 power on all the VDD pins, GND on all the GND pins

All DIOs are configured as inputs on FPGA

 

I monitor the nCS,SCL, DIN and DOUT on scope and the current consumption from power supply in 0.1mA resolution.

 

Without the ADIS mounted, the FPGA consumes about 2.5mA

Adding the ADIS, the current goes up, but seems to cycle between 5mA and 11mA,  quite quickly i.e. cycles in about 2s

 

It seems as if the ADIS never starts up.

 

I am communicating with the ADIS on SPI very quickly after power up. I could find no data in the datasheet as to how long the reset signal must be asserted to ensure proper reset, that is the reason I have then changed it to not reset the ADIS from FPGA.

 

So I started looking at the current pulses on the scope and have determined the following:

  1.   The pulse duration is about 1ms
  2. The pulse repeats every 324ms

 

UPDATE1:

So I erased the FPGA, causing all pins to be tristate, so for ADIS it means only power is applied. Still those current pulses are present.

I checked all the signals and they are high, EXCEPT for DIO1 which contains some pulse train coinciding with the current pulses, but active for longer period.

 

UPDATE2:

Created a power on reset of low for 1.024us from FPGA to ADIS, no change in output.

What is the expected current draw from this device, the datasheet indicates the typical powered up as 197mA, which is why I believe the device is not starting up.

The Sleep current is given as 12mA, which is consistent (sort of) with the current used by the device at the moment.....BUT why would it be sleeping?

 

UPDATE 3:

So the datasheet state:

To awaken the device from sleep or power-down mode, use one of the following options to restore normal operation:

  •   Assert CS from high to low.
  •   Pulse RST low, then high again.
  •   Cycle the power.

So I update the FPGA code to make CS low all the time, till using less than 12mA.

 

 

Any ideas would be appreciated. If need be, I can upload SPI signals, but at the moment it feels as if the ADIS is not powering up correctly.

 

Ivor

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