When the AD6659 is setup for interleaved outputs, on which pins will the DCO and Data be driven?
The Interleaved output mode is enabled globally onto both output channels simultaneously via register 0x14, bit 5. The DCO and interleaved DATA will be avail on both output ports. The undesired channel output (DATA and DCO) can then be disabled by selecting the desired Channel (A or B) Index at 0x05,
bits 1-0, then writing a 1 to local (channel specific) OEB register 0x14, bit 4.
The default operation of interleaved (DDR) mode outputs chA port data as ADC_A/B as shown in d/s
fig 3 and outputs chB port data as ADC_B/A (not shown in d/s), although this can be reconfigured by
the customer to either A/B or B/A sequence using the “output Invert” bit 0x14, bit 2.
So in interleave mode (d/s fig 3) the respective A or B data is output for only ½ of the CLK period,
latched by both the rising and falling edges as opposed to the non-interleaved mode shown in fig 2.
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