I'm writing code for the blackfin Bf-537E. Now my code doesn't fit in the L1 cache memory. So a lot of functions are now moved to the SDRAM0_bank0. When executing the code, I now get an exception.
I tried to play with the settings in project options (Visual DSP), but I get no sollution. I managed to put the code in bank 3 instead of bank 0, but als that doesn't do the trick.
I've also created a code that could fit in cache and I've made a variable big enouph (2048B) and I've put this in the Ram bank1. Reading and writing from it works.
It looks like that if code is put in the sdram, the processor is not able to execute it.
NB: I'm also using the EBIU asynchronous memory for communicating with an FPGA. This works good.
Somebody knows what the problem is?