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Sampling Frequency Increase in ADFMCOMMS-1

Question asked by odiz on Dec 9, 2013
Latest reply on Jan 28, 2014 by DragosB


I have been using FMCOMMS-1 with ZedBoard. I am trying to implement a direct baseband sampling application using AD9643 with RF components bypassed (by solders) on the FMCOMMS-1 Board. I have been using the reference codes provided in AD-Wiki page to get samples from ADC and observe the samples in SDK. I take samples from ADC and downsample them by 4 before giving the samples to the DMA Core in HDL, by means of a simple block I put in the reference HDL code in front of the DMA Core (necessary signalling with DMA Core, such as valid signal, clock signal, etc., is taken into consideration). I use the same clock frequencies for interfaces clocks of adc_core and dma_core in XPS design as given in the reference design. Everything works perfectly fine (I observe the samples from SDK as I expect them to be) until I increase the sampling frequency of ADC to 178.5 MHz. After this frequency the samples are distorted. Is this possibly related to the clock frequencies of interfaces of adc_core and dma_core that I kept the same? If not, what may be the cause of this problem? Thank you very much.