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Strange problem when changing CPLB table

Question asked by gpetrowitsch on Jun 21, 2010
Latest reply on Jun 24, 2010 by gyi

Dear all,

 

I've got a strange problem with my proprietary BF548 system, when I change

some settings in the CPLB tables.

 

If I use these settings for the data CPLB table, all works fine:

 

cplb_entry dcplbs_table[] = {
  /*$VDSG                           */
  /* This code is preserved if the CPLB tables are re-generated.  */

   // L1 Data A & B, (set write-through bit to avoid 1st write exceptions)
   {0xFF800000, (PAGE_SIZE_4MB | CPLB_DNOCACHE | CPLB_LOCK | CPLB_WT)},

   // L2 SRAM - possible stack use so locked 
   {0xFEB00000, (PAGE_SIZE_1MB | CACHE_MEM_MODE | CPLB_LOCK)},

 

   //  64 MB (Maximum 512MB) DDR1 memory space
   // NOTE: if we don't lock the first CPLBs, we get some odd error 

   //  (L1_code_cache_enable_when_L1_used_for_code)
   //  but only after emulator stops execution and single stepping is done

   //  in function adi_ebiu_ApplyDDRConfig
   {0x00000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_DIRTY | CPLB_LOCK)}, 
   {0x00400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_DIRTY | CPLB_LOCK)}, 
   {0x00800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_DIRTY | CPLB_LOCK)}, 
   {0x00C00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_DIRTY | CPLB_LOCK)},

   {0x01000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_DIRTY)},
   {0x01400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_DIRTY)},
   {0x01800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_DIRTY)},
   {0x01c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_DIRTY)},

   {0x02000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_DIRTY)},
   {0x02400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_DIRTY)},
   {0x02800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_DIRTY)},
   {0x02c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_DIRTY)},
   {0x03000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_DIRTY)},
   {0x03400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_DIRTY)},
   {0x03800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_DIRTY)},
   {0x03c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_DIRTY)},

   // Async Memory Bank 3

"skipped all the settings for async memory banks"
   
   // CPLBs covering 64MB
   {0x2c000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2c400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},

   // 4kB Boot ROM
   {0xEF000000, (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_VALID | CPLB_USER_RD)},

   // end of section - termination
   {0xffffffff, 0}, 
   /*$VDSG                           */
}; /* dcplbs_table */

 

But if I remove the CPLB_LOCK bits from the first 4 entries associated with the

DDR1 memory, the system does very strange things. I suppose it

executes code from uninitilized memory, because the calling stack looks

like this.

 

_adi_ebiu_ApplyDDRConfig()

<is_icplb_miss + 0x2>

<skip_dcache_checks + 0x2e>

<skip_dcache_checks + 0x10e>

<.end_of_user_code2 + 0xa>

<___wab2 + 0x16560>

<___wab2 + 0x1681e>

<___wab8 + 0xbeeeef3a>

<___wab8 + 0xbeeeef3a>

 

Often (but not always), when I stop execution with the emulator and single step,

it seems to hang in a function called adi_ebiu_ApplyDDRConfig in file adi_ebiu_asm.asm.

But through single stepping it soon reaches some jump, which jumps on itself and has the label

"l1_code_cache_enable_when_l1_used_for_code". It never reaches this point, when I don't

single step - no matter how long I wait before stopping execution.

 

I removed the CPLB_LOCK bits, because I read in the forum, that only CPLBs

associated with internal memory should have these bit enabled.

 

I'm a bit uncomfortable with just leaving the CPLB_LOCK bits there, because

it's ugly to serve some uniform chunk of memory (my 64MBytes) with un-uniform

settings (some CPLBs locked, some not).

 

Can somebody explain, what happens here?

 

Regards,

Gerhard

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