I would like to make sure spec of ADuM4190.
1. Regarding about Figure 26
CH2 is EAout 50mV/div
CH3 is EAout2 20mV/div
These are same division level signals.
These scale were mixed up?
It is 50mV/uSec slew rate? or 125mV/uSec?
2. Regarding about Internal update timing.
Figure 25 and 26 say internal DCDC will update about 2.5uSec each.
It means 400KHz BW ?
Datasheet say, over 3uS no signal then high impedance, but I couldn’t find normal update frequency of the internal DCDC.
What Frequency of internal clock?
Can control that timing to noise management?