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The SPI Master Mode Boot from SPI Memory

Question asked by zcyhansen on Dec 6, 2013
Latest reply on Dec 6, 2013 by zcyhansen

hello

    When I use the bf537, and I set the bf537 boot from SPI . There is an question that confuse me.

    When I refer the bf537 datasheet, the datasheet says as follow :

 

For SPI master mode boot (BMODE = 011), the boot kernel assumes that the

SPI baud rate is SCLK/(2 x 133) Kbit/s. SPI serial EEPROMs that are

8-bit, 16-bit, and 24-bit addressable are supported. The SPI uses the PF10

output pin to select a single SPI EEPROM device. The SPI controller

submits successive read commands at addresses 0x00, 0x0000, and

0x000000 until a valid 8-, 16-, or 24-bit addressable EEPROM is

detected. It then begins clocking data into the beginning of L1 instruction

memory.

 

there is a centence that I marked with red color, say the PF10 is uesd to select the EEPROM device.

So can someone tell me ,  can I use other pin (for example PF5)  to select the EEPROM? And how to do it?

Second. is that  each processor  use a fixed pin to select the EEPROM when boot from SPI , and can not change?

 

thank you very much!!

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