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PLL don't work right

Question asked by bookevg on Jun 18, 2010
Latest reply on Jun 22, 2010 by bookevg

I have my target board with ADSP-21375

CLKIN = 40MHz

I write a code:

//-------------------------------------------

volatile u32 temp;
// Core clock =  ( (40.000MHz / 2) * 13) / 1 = 260.000 MHz run SDRAM at 130
*pPMCTL    = (INDIV | PLLM13 | PLLD1 | DIVEN | SDCKR2);     // Input divider | PLL Multiplier 48;
temp          = *pPMCTL;
temp                  |= PLLBP;
temp                  ^= DIVEN;
  *pPMCTL          = temp;
// Wait at least 4096 cycles for the pll to lock
for(temp     = 0; temp < (u32)5000; temp++ )
{     asm("nop;");     }
*pPMCTL ^= PLLBP;

 

//Generating Code for connecting : SPORT0_DA to DAI_PIN16
SRU (HIGH, PBEN16_I);
SRU (SPORT0_CLK_O, DAI_PB16_I);
*pSPCTL0     = 0;
*pSPMCTL0     = 0;
*pDIV0          = (0x000F << 16) | (0x0006 << 1);     //
*pSPCTL0     = (SPEN_A | SLEN16 | BHD | IFS | ICLK | SPTRAN);
while (1)
{
{     asm("nop;");     }
}

//-------------------------------------------

I watch oscilloscope DAI_PB16_O and saw 714.294kHz = PCLK / (4*(6+1)) = 20MHz / (4*(6+1))

Why PCLK = 20MHz?

PCLK must be 260.000 MHz/2 = 130.000 MHz

I used ADZS-HPUSB-ICE and ADSP-21375BSWZ-2B 1496059.1. 0.0  #0835

When I stop my program and output Window-Power Management and Control I see PLLBP=0, but  PCLK = 20MHz = 40MHz/2

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