I am trying to make an application based on Analog Devices' ADV212 codec which must compress/decompress full HD interlaced video (1080i-50Hz).
I use 2 ADV212 chips for compression and 2 chips for decompression according to the recommendations. All those chips have speed grade 150MHz.
The pair of the encoding chips and the pair of the decoding chips are connected in the circuit via HDATA port and VDATA port to FPGA.
I use only 16 bits of the HDATA bus (i.e. pins HDATA[15..0]) in order to minimize the pin count. I use DMA channel in order to read/write JPEG2000 data.
Unfortunately, I cannot launch the pair of decoding chips. I use Application Note AN-796 as a guide. I configured the registers of the decoding chips, detected and cleared the SWIRQ0 interrupt and applied the JC2 stream via HDATA[15..0] bus using burst DMA. The decoding chips repeatedly assert DREQ for a few seconds and stop. DREQ becomes inactive. After a few seconds, I check SWIRQ1 by reading the register (when DMA activity is no longer present according to oscilloscope), but it does not become active. INT is not active, either.
Please note that I apply streaming J2C to the decoders. That is to say, J2C data may arrive at the decoders' inputs at any moment and the first word of JPEG2000 data is not necessarily the first word in the JPEG2000 header. But the stream in continuous.
What might be wrong ?