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ADF4350 Intermittent Locking

Question asked by jbaker on Dec 3, 2013
Latest reply on Feb 13, 2014 by icollins

Hi,

 

I have designed a board that utilizes two ADF4350 chips. Both are to work at a single frequency, one at 148.405 MHz and the other at exactly twice the frequency of the first (296.81 MHz in this case). The relative phases between the two need to be adjustable, so I have both chips sharing the same reference signal. I was careful in the board layout to make both REF traces equal lengths.

 

Before I made this board, I played around with the ADF4350 evaluation board (EVAL-ADF4350EB2Z, the one that corresponds with UG-110). The board locked to virtually all frequencies that I tried without fail (the one exception I found was at 148.000 MHz, which is not a big deal). So when designing my board, I modeled the ADF4350 circuits in my board after the eval board schematic in UG-110. So when I tested my board I was suprised to find that the lower frequency ADF4350 circuit (148.405 MHz) had trouble locking. I had to reprogram the registers multiple times till I finally got it to lock. The higher frequency ADF4350 circuit (296.81 MHz) had no trouble locking. The settings I used for both the eval board and my board are as follows:

 

All voltage supplies set to 3.3V

Frequency: 148.405 MHz

Reference Frequency: 10 MHz

Phase-Detector Frequency: 5 MHz

Reference div by 2

Prescaler: 4/5

Feedback Signal: Divided

Charge Pump Current: 2.50

LDF: FRAC-N

LDP: 10ns

LD Pin Mode: Digital Lock Detect

R5: 0x00580005

R4: 0x0042843C

R3: 0x0001001B

R2: 0x01004E42

R1: 0x00009F41

R0: 0x000E9548

 

The loop filter I used is a third order integrator, the same topology as on the eval board. Although the eval board's loop filter worked with my desired settings, for my board I decided to calculate new loop filter values tailored to my specific design using ADIsimPLL.

C1 = 1nF

R1 = 845

C2 = 15nF

R2 = 1.87k

C3 = 470pF

Needless to say, when I tested my board I was only getting lock intermittently (the higher frequency synthesizer locked fine). I then realized that I had almost certainly used ADIsimPLL wrong. So I replaced my loop filter components to the same values that are listed for the eval board in UG-110:

C1 = 1.5nF

R1 = 430

C2 = 22nF

R2 = 820

C3 = 680pF

To my surprise, the ADF4350 was still having trouble consistently locking even though that same loop filter worked on the eval board. So i turned to ADIsimPLL again and I think I entered all my settings correctly to get a loop with bandwidth of 35kHz and phase margin 45 degrees (although I may be entirely wrong again):

PFD = 5MHz

Vp = 3.3V

CP Current = 2.5mA

C1 = 510pF

R1= 1.87k

C2 = 6.8nF

R2 = 3.6k

C3 = 240pF

This new filter offered no improvement to the locking issue and I am now at a loss of what the problem is and how to fix it. Does anyone have any ideas of what the problem could be?

 

Jesse

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