I am working with ADF4158 Evaluation board. I just downloaded a newer version of ADF41589 PLL software (Revision 4.9.0). The main controls section Register 4 doesn't allow me to choose a CLK2 Div value of less than 2. The datasheet doesn't mention any restriction on the CLK2 divider value. is this an error in the control software? I am planning to use both CLK1 and CLK2 divider values of 1 so that i can get 1 ms/ramp with smallest step size. I've attached the settings I am using.
Thanks for a prompt response.