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AD-FMCOMMS1-EBZ input modification

Question asked by steve_c on Nov 28, 2013
Latest reply on Dec 18, 2013 by charlyelkhoury

Hi once again,

 

I am attempting to connect a simple hardware module to produce a square wave output from the reference design into the DAC, and then view this output on the ADC using ChipScope. The hardware module provides 16 single-ended signals to the design. The DDS produces a sine wave and so will not work for this, and the VDMA is unavailable. What signals exactly should I connect to?

 

Carrier: VC707

Reference Design: v2, Nov.20, 2013

Software: Standard drivers from Nov. 20, 2013 with dac_dma_setup deactivated.

Simple test: Change the signal values entering the DAC using constants.

Details: The connections in axi_ad9122_core.v were modified as:

  always @(posedge dac_div_clk) begin

.

.

//VDMA part unchanged

.

.

    end else begin

      dac_data_i0 <= 16'h8000;//dac_dds_data_0_0_s;

      dac_data_i1 <= 16'h8000;//dac_dds_data_0_1_s;

      dac_data_i2 <= 16'h7FFF;//dac_dds_data_0_2_s;

      dac_data_i3 <= 16'h7FFF;//dac_dds_data_0_3_s;

      dac_data_q0 <= 16'h8000;//dac_dds_data_1_0_s;

      dac_data_q1 <= 16'h8000;//dac_dds_data_1_1_s;

      dac_data_q2 <= 16'h7FFF;//dac_dds_data_1_2_s;

      dac_data_q3 <= 16'h7FFF;//dac_dds_data_1_3_s;

    end

 

This resulted in a fuzzy sine output, rather than the clean sine output from when the dds signal is connected appropriately.

 

Thanks,

Stephen

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