, I have the following question(s) about AD7625 Datasheet.
- On page 5, timing specifications, tmsb is stated as 145 nm(max)
- If you look at page 19 timing diagram from echoed-clock interface mode, tmsb has to elapse before I can burst CLK+ and CLK- from the digital host (FPGA in my case) to latch the data out
- Should I look at tmsb spec as a time that should not be exceeded?
- If so, what is the minimum value of tmsb (not stated in the datasheet). I ask this because, for Sample_N, acquisition has to start before the clock burst otherwise I start reading invalid MSB. So if 145ns is the maximum delay, what is the minimum delay? Or in other words what is the relationship between tmsb and rising edge of T_ACQ?