We are currently designing a product with the SSM2604 audio codec. My question is regarding the core clock frequency. On page 4 of the datasheet (Rev A) it is clearly stated that the core clock tolerance is 8 - 13.8MHz. This indicates that an MCLK of 27.6MHz would be the maximum input allowed (providing that CLKDIV2 = 1), however in "Table 26. Sampling Rate Lookup Table, USB Disabled (Normal Mode)" MCLK rates of up to 36.864 MHz are defined. Which of these figures is correct?
Secondly, assuming that an MCLK of over 27.6MHz can be used, is it possible to input 30MHz to achieve a core clock of 15MHz? This would not allow the use of standard sample rates (using the SR bits) but this is not a requirement for this design.
I hope someone can clarify this for me. Many thanks in advance.