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ad9957 eval board: PDCLK/TXENABLE metstability issue?

Question asked by KerwoodDerby on Jun 16, 2010
Latest reply on Jun 16, 2010 by DSB

I'm pursuing an inquiry involving the AD9957's generation of a pulsed waveform and its simultaneous acquisition by a high-speed ADC. However, all the operations have to occur coherently, so I've slaved the ADC sample clock to the AD9957's PDCLK. I also had to OR the Altera FPGA's TX_ENABLE signal into the IO_UPDATE signal it generates, as well as set bit 13 in CFR1, so that the pulse would begin with identical phase each time. This works ok. Data arrives in QDUC mode.


But my remaining problem is that the time between the TX_ENABLE edge and the start of the synthesized pulse (seen at FILTERED IOUT) is varying discretely between one delay and another delay which is one PDCLK period later, suggesting a metastability issue. When I look at the TX_ENABLE signal supplied by the Altera FPGA, I see that it rises at pretty much the same time as PDCLK, creating a setup time violation.


Curiously, if I "cheat" this by applying a series R and shunt C to the TX_ENABLE signal on its way to the AD9957, it does shift the phase of TX_ENABLE relative to PDCLK away from the violation condition, but I get still get no relief in the apparent metastability behavior.


Any ideas on where to look next? Thanks.