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AD9287 clock derived from an FPGA - issues ?

Question asked by timbat on Nov 19, 2013
Latest reply on Dec 5, 2013 by timbat

I have inherited a design where the ADC clock is derived from an FPGA.

 

I am worried, when the FPGA is being programmed, the clock stops as the I/O isn't get enabled. The other possibility is the input clock into the FPGA can be switched off and then the output is indeterminate.

 

I am having issues where the test signals from the ADC are correctly received by the FPGA (PN, two state etc) but occassionally the live signal has a weird bandpass when we FFT the data.

 

Is it ok if the clock stops ? Or changes frequency ?

 

Can you suggest what SPI commands should be issued after the FPGA gains lock and starts outputting a clock to the ADC ?

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