I have inherited a design where the ADC clock is derived from an FPGA.
I am worried, when the FPGA is being programmed, the clock stops as the I/O isn't get enabled. The other possibility is the input clock into the FPGA can be switched off and then the output is indeterminate.
I am having issues where the test signals from the ADC are correctly received by the FPGA (PN, two state etc) but occassionally the live signal has a weird bandpass when we FFT the data.
Is it ok if the clock stops ? Or changes frequency ?
Can you suggest what SPI commands should be issued after the FPGA gains lock and starts outputting a clock to the ADC ?