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Requirement of input CLK signal of ADV7511W.

Question asked by Tamu on Nov 18, 2013
Latest reply on Nov 20, 2013 by Tamu



I have questions about input clock pin (53pin) of ADV7511W.

Is there any requirement of high interval time and low interval time of input CLK signal?
For example, what percent (%) of clk period should be high/low interval?
We assume 3.3V I/O. So please tell us the spec for 3.3V CLK signal.


Thank you.
Best regards.