ADuC7061 has internal PLL and it generates 10.24MHz to be offered to core.
I wonder what the variation of PLL's output clock rate is over temperature.
This is specified for the whole temperature range from -40°C to 125°C as per data-sheet page 8 in relationship to the used clock source - if the on-chip 32kHz oscl.is used this is +/- 3% or better if you use a external 32kHz crystal.
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On-chip oscilator has the range of variation of +/- 3%. Is the variation related to temperature or independant of temperature?
it is max. and related to the whole temperature range. For a stable temperature the frequency should be stable - of course the PLL has some minor (ps - pico second) jitter. But this jitter you have as well with a external crystal.
Better performance you get with the new ADuCM360/361 - this has a 16MHz oscillator and no PLL - so less jitter and it is 1% accurate over the whole temperature range.
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