Greeting support team!
I am using AD9915 evaluation board and trying to program the DDS chip from parallel port using FPGA.
I want to use DRG to generate a linear frequency modulated signal, it is strange that the DROVR pin did not send out correct signals. After power on the DDS evaluation board, the DROVR kept low for short period and turned to high forever.
1) If I enable both "digital ramp no-dwell high" and "no-dwell low", the DDS can output correct LFM signal, but the DROVR is always high instead of "producing a positive pulse each time the DRG output reaches either of the programmed limits". 2) If I just enable "digital ram no-dwell high", the DDS output signal kept at low limit frequency and did not response to the change of DTRL signal, the DROVR kept high.
I have enabled the DRG output in CFR register, the DDS chip acts like that it does not respond to DTRL signal and DROVR is always high. Do you have any suggestions? Thanks in advance.