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ADV7343 CVBS out configurations

Question asked by Lix on Nov 14, 2013
Latest reply on Nov 14, 2013 by GuenterL

I am trying to setup my ADV7343 in different CVBS modes and I believe I have the right register configurations. I have not been able to verify this yet as I am still waiting for the hardware to play with.

 

The configuration I am having difficulty with are NTSC/PAL mono and PAL 60, I think I have solutions just would like verification before I gte the hardware

.

Does anyone know if the ADV7343 can do 'PAL Comb. N'?

 

Cheers

 

Lix

 

 

I2C register configrations


I2C_config_s DEFAULT_CONFIG_NTSC4_43 []

{

    { 0x17, 0x02}, // Software reset

    { 0x00, 0x20}, // Power up DACs and PLL 0x1C on example 0x20 needed   

    { 0x01, 0x00}, // SD only mode   

    { 0x80, 0x10}, // SSAF Luma filter enabled, NTSC mode

    { 0x82, 0xCB}, // Step control on, pixel data valid, pedestal on, PrPb SSAF on, CVBS out.

    { 0x87, 0x00}, // Disable autodetect mode

    { 0x88, 0x10}, // 10 bit input enabled

    { 0x8C, 0x8C}, // FSC for NTSC 443

    { 0x8D, 0x43}, //

    { 0x8E, 0x0A}, //

    { 0x8F, 0x2A} //

};

 

I2C_config_s DEFAULT_CONFIG_PAL_60 []

{

    { 0x17, 0x02}, // Software reset

    { 0x00, 0x20}, // Power up DACs and PLL 0x1C on example 0x20 needed   

    { 0x01, 0x00}, // SD only mode   

    { 0x80, 0x11}, // SSAF Luma filter enabled, PAL mode

    { 0x82, 0xCB}, // Step control on, pixel data valid, pedestal on, PrPb SSAF on, CVBS out.

    { 0x87, 0x00}, // Disable autodetect mode

    { 0x88, 0x10}, // 10 bit input enabled

    { 0x8C, 0x8C}, // FSC for NTSC 443

    { 0x8D, 0x43}, //

    { 0x8E, 0x0A}, //

    { 0x8F, 0x2A} //

};

 

I2C_config_s DEFAULT_CONFIG_NTSC_mono []

{

    { 0x17, 0x02}, //Software reset.

    { 0x00, 0x20}, //Turn DAC 1 enabled rest turn off. PLL enabled (16×).

    { 0x02, 0x30}, //Puts Y signal of YPrPb on output. Black and white signal.

    { 0x01, 0x00}, //SD input mode.

    { 0x80, 0x10}, //NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled.

    { 0x82, 0xC9}, //Pixel data valid. YPrPb and CVBS/Y-C out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled.

    { 0x87, 0x80}, //RGB input enabled.

    { 0x88, 0x10}, //24-bit RGB input enabled

    { 0x8A, 0x0C} //Timing Mode 2 (slave). HSYNC/VSYNCsynchronization

}

 

I2C_config_s DEFAULT_CONFIG_PAL_mono []

{

    { 0x00, 0x20}, //Turn DAC 1 enabled rest turn off. PLL enabled (16×).

    { 0x01, 0x00}, //SD input mode.

    { 0x02, 0x30}, //Puts Y signal of YPrPb on output. Black and white signal.

    { 0x17, 0x02}, //Software reset.

    { 0x80, 0x11}, //PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled.

    { 0x82, 0xC1}, //Pixel data valid. YPrPb and CVBS/Y-C out. SSAF PrPb filter enabled. Active video edge control enabled.

    { 0x87, 0x80}, //RGB input enabled.

    { 0x88, 0x10}, //24-Bit RGB input enabled

    { 0x8A, 0x0C} //Timing Mode 2 (slave). HSYNC/VSYNC synchronization.

};

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