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AD-FMCOMMS1-EBZ on ZC706, ad9548 not locking to reference

Question asked by skp on Nov 13, 2013
Latest reply on Jan 14, 2014 by DragosB

Hi

 

We need to get 2 boards [NOT MIMO, One is TX other RX] either synchronized to single reference or synced to independent 0.5 ppm references.

However we noticed that even for the default builds (both version 1 HDL and Version 2 HDL) the boards starts up widely different frequencies ( 4 - 5 KHz apart @ 2.4GHz). Suspecting that the PLLs are not locking (though the software status on the /sys shows them to be locked) we modified the HDL to be able to switch the reference between the FPGA generated 303 MHz reference and external (30.3 MHz) clock fed through SMA connectors. Found that the RF output was not locked to the 30.3 MHz going to the ad9548.

 

Further investigation checking the output of ad9548 (122.8 MHz) confirmed that it was free running. This was again confirmed by rebuilding the kernel after adjusting the FTW in the ad9548.c. That is the frequency changed, confirming it is free running, and not locked to the REFA input.

 

Dumping the status registers to kernel log again confirmed this!

 

ad9548 spi32765.2: Rev. 0xC6 (PLATFORM_XCOMM1_0_V2_9548fix) probed

ad9548 spi32765.2: ad9548 reg [0D01] = 11

ad9548 spi32765.2: ad9548 reg [0D02] = 00

ad9548 spi32765.2: ad9548 reg [0D03] = 00

ad9548 spi32765.2: ad9548 reg [0D04] = 00

ad9548 spi32765.2: ad9548 reg [0D05] = 00

ad9548 spi32765.2: ad9548 reg [0D06] = 00

ad9548 spi32765.2: ad9548 reg [0D07] = 00

ad9548 spi32765.2: ad9548 reg [0D08] = 00

ad9548 spi32765.2: ad9548 reg [0D09] = 00

ad9548 spi32765.2: ad9548 reg [0D0A] = 01

ad9548 spi32765.2: ad9548 reg [0D0B] = 00

ad9548 spi32765.2: ad9548 reg [0D0C] = 86

ad9548 spi32765.2: ad9548 reg [0D0D] = 07

ad9548 spi32765.2: ad9548 reg [0D0E] = 07

ad9548 spi32765.2: ad9548 reg [0D0F] = 07

ad9548 spi32765.2: ad9548 reg [0D10] = 07

ad9548 spi32765.2: ad9548 reg [0D11] = 07

ad9548 spi32765.2: ad9548 reg [0D12] = 07

ad9548 spi32765.2: ad9548 reg [0D13] = 07

ad9548 spi32765.2: ad9548 reg [0D14] = 00

ad9548 spi32765.2: ad9548 reg [0D15] = 00

ad9548 spi32765.2: ad9548 reg [0D16] = 00

ad9548 spi32765.2: ad9548 reg [0D17] = 00

ad9548 spi32765.2: ad9548 reg [0D18] = 00

 

Note the 0x0D0A value 01 which reports the DPLL is not locked and free running!? Also note the 0x0D0C value of 86 which seems to indicate that the reference is valid and fault at the same time (?!! May be it was validated then faulted!).

 

Tried to override the validation logic, but with no effect!

 

The ad9548 programming was not changed from the reference design (and is copied below).

 

We are seeing this behavior  on all the 3 boards we are currently using hence doesn't seems to be a board specific problem!

 

Any help (need it urgent) to get these boards to lock to stable references will be greatly appreciated!

 

[Again our use case is not MIMO, but as independent transcievers; just to avoid possible confusion as syncing 2 boards for MIMO was earlier answered in the forum].

 

skp

 

 

static const unsigned short ad9548_regs[][2] = {

          {0x0000, 0x30}, /* Reset */

          {0x0000, 0x10},

          {0x0000, 0x10},

          {0x0000, 0x10},

          {0x0000, 0x10},

          {0x0000, 0x10},

          {0x0100, 0x18}, /* System clock */

          {0x0101, 0x28},

          {0x0102, 0x45},

          {0x0103, 0x43},

          {0x0104, 0xDE},

          {0x0105, 0x13},

          {0x0106, 0x01},

          {0x0107, 0x00},

          {0x0108, 0x00},

          {0x0005, 0x01}, /* I/O Update */

          {0x0A02, 0x01}, /* Calibrate sysem clock */

          {0x0005, 0x01},

          {WAIT_B, 0x00},

          {0x0A02, 0x00},

          {0x0005, 0x01},

          {0x0208, 0x00}, /* IRQ Pin Output Mode */

          {0x0209, 0x00}, /* IRQ Masks */

          {0x020A, 0x00},

          {0x020B, 0x00},

          {0x020C, 0x00},

          {0x020D, 0x00},

          {0x020E, 0x00},

          {0x020F, 0x00},

          {0x0210, 0x00},

          {0x0211, 0x00}, /* Watchdog timer */

          {0x0212, 0x00},

          {0x0213, 0xFF}, /* Auxiliary DAC */

          {0x0214, 0x01},

          {0x0300, 0x29}, /* DPLL */

          {0x0301, 0x5C},

          {0x0302, 0x8F},

          {0x0303, 0xC2},

          {0x0304, 0xF5},

          {0x0305, 0x28},

          {0x0307, 0x00},

          {0x0308, 0x00},

          {0x0309, 0x00},

          {0x030A, 0xFF},

          {0x030B, 0xFF},

          {0x030C, 0xFF},

          {0x030D, 0x00},

          {0x030E, 0x00},

          {0x030F, 0x00},

          {0x0310, 0x00},

          {0x0311, 0x00},

          {0x0312, 0x00},

          {0x0313, 0x00},

          {0x0314, 0xE8},

          {0x0315, 0x03},

          {0x0316, 0x00},

          {0x0317, 0x00},

          {0x0318, 0x30},

          {0x0319, 0x75},

          {0x031A, 0x00},

          {0x031B, 0x00},

          {0x0306, 0x01}, /* Update TW */

          {0x0400, 0x0C}, /* Clock distribution output */

          {0x0401, 0x03},

          {0x0402, 0x00},

          {0x0403, 0x02},

          {0x0404, 0x04},

          {0x0405, 0x08},

          {0x0406, 0x03},

          {0x0407, 0x03},

          {0x0408, 0x03},

          {0x0409, 0x00},

          {0x040A, 0x00},

          {0x040B, 0x00},

          {0x040C, 0x03},

          {0x040D, 0x00},

          {0x040E, 0x00},

          {0x040F, 0x00},

          {0x0410, 0x00},

          {0x0411, 0x00},

          {0x0412, 0x00},

          {0x0413, 0x00},

          {0x0414, 0x00},

          {0x0415, 0x00},

          {0x0416, 0x00},

          {0x0417, 0x00},

          {0x0500, 0xFE}, /* Reference inputs */

          {0x0501, 0x00},

          {0x0502, 0x00},

          {0x0503, 0x08},

          {0x0504, 0x00},

          {0x0505, 0x00},

          {0x0506, 0x00},

          {0x0507, 0x00},

          {0x0600, 0x00}, /* Profiles are 0x0600-0x07FF */

          {0x0601, 0x55}, /* Profile 0 */

          {0x0602, 0xA0}, /* 30MHz input from FPGA, 122.880MHz output clock */

          {0x0603, 0xFC},

          {0x0604, 0x01},

          {0x0605, 0x00},

          {0x0606, 0x00},

          {0x0607, 0x00},

          {0x0608, 0xE8},

          {0x0609, 0x03},

          {0x060A, 0x00},

          {0x060B, 0xE8},

          {0x060C, 0x03},

          {0x060D, 0x00},

          {0x060E, 0x88},

          {0x060F, 0x13},

          {0x0610, 0x88},

          {0x0611, 0x13},

          {0x0612, 0x0E},

          {0x0613, 0xB2},

          {0x0614, 0x08},

          {0x0615, 0x82},

          {0x0616, 0x62},

          {0x0617, 0x42},

          {0x0618, 0xD8},

          {0x0619, 0x47},

          {0x061A, 0x21},

          {0x061B, 0xCB},

          {0x061C, 0xC4},

          {0x061D, 0x05},

          {0x061E, 0x7F},

          {0x061F, 0x00},

          {0x0620, 0x00},

          {0x0621, 0x00},

          {0x0622, 0x0B},

          {0x0623, 0x02},

          {0x0624, 0x00},

          {0x0625, 0x00},

          {0x0626, 0x26},

          {0x0627, 0xB0},

          {0x0628, 0x00},

          {0x0629, 0x10},

          {0x062A, 0x27},

          {0x062B, 0x20},

          {0x062C, 0x44},

          {0x062D, 0xF4},

          {0x062E, 0x01},

          {0x062F, 0x00},

          {0x0630, 0x20},

          {0x0631, 0x44},

          {0x0005, 0x01}, /* I/O Update */

          {0x0A0E, 0x01}, /* Force validation timeout */

          {0x0A0D, 0x03},

          {0x0A01, 0x00},

          {0x0005, 0x01}, /* I/O Update */

          {0x0A02, 0x02}, /* Sync distribution */

          {0x0005, 0x01},

          {0x0A02, 0x00},

          {0x0005, 0x01},

          {0x0A0F, 0x00},

          {0x0A10, 0x01},

          {0x0005, 0x01}, /* I/O Update */

};

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