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AD9122 sync enable and fifo soft align ack issues

Question asked by smoses on Nov 12, 2013
Latest reply on Nov 18, 2013 by smoses

Hi there,


I have an FMC board with an AD9122 device that I'm trying to bring up. I have verified my SPI interface works properly with the part by reading/writing various DAC registers. I started programming the DAC in FIFO rate mode following figure4 flowchart in AN-1093 but was never able to get the sync lost/lock bits to set even after changing the sync edge register. Then I realized that the sync enable bit(7) and Sync Averaging bit(2:0) of register 0x10 were always readback as 0s. The two other fields in the same register at bits 3 and 6 always matched what was written to them. Any idea what is going on here?


I also tried to bring up the DAC in the synchronization off mode following figure2 flowchart in AN-1093, this time the problem was with the fifo soft align ack (bit(2) of register 0x18). After setting fifo soft align request (bit(1) of register 0x18), the ack was not received. Any idea what's causing this?


Another strange thing I noticed is the fifo thermometer readback always returned 0x55.


Thanks in advance for any help you can provide.