I have questions about DDR operation of ADV7181D.
Please refer attached file "ADV7181D_DDR_mode_Evaluation.xlsx".
The LLC output is 54MHz.
The only rising edges of LLC are used.
It's not same as Figure 68: DDR Principle of Operation of HW manual.
It does not seem DDR I/F.
Is this correct operation?
Do we have to set other register for DDR operation?
Is there any register to divide to half for LLC clock?