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ADF4351 serial port protocol

Question asked by PDS on Nov 12, 2013
Latest reply on Nov 13, 2013 by icollins

While the LE input is held low, and more than thirty-two rising edges are sent to the CLK input, then subsequently the LE input brought high, what will be the final outcome of data loaded into the register file of the ADF4351? Will the transaction be completely ignored? Will the transaction be accepted, taking only the first 32 bits of data sent to the device? Or will the transaction be accepted, taking only the last 32 bits of data sent to the device?

 

Alternately, is there any means to operate the serial port in a "dual sixteen" manner? In other words, two entirely separate transactions where the LE input is asserted and released during each of two sets of sixteen clocks as shown?

 

       /--\    /--\                   /--\    /--\

CLK ---/    \--/    \--..16..---------/    \--/    \--..16..

 

    -\                         /---\                         /-----

LE    \-----------------------/     \-----------------------/

Outcomes