I have some questions about the ADV7181D timing.
Setup : Custom hardware (hosting an ADV7181D). The ADV7181D indirectly drives an LCD, allowing us to view the ADV7181D's video output. The ADV7181D is driven by one of four PAL video generators. All PAL sources have been verified to work (they all successfully drove an independent monitor).
Our situation: The ADV7181D is able to lock successfully onto some, but not all of our lab PAL video sources. On a scope, the differences between these video sources are in the timing of non-active video portions of the signal.
Specifically, the ADV7181D has trouble locking onto the video sources with (relatively) slow hsync rise and fall times.
Additionally, the ADV7181D has trouble locking onto the video sources with a (relatively) short back-porch preceeding the color burst (despite the fact that the color burst frequency measures ok).
Are there minimum timing requirements for front porch, back porch, hsync width, hsync rise and fall time, and blanking period for composite video?
Is there a minimum/maximum timing requirement for the period between the end of the hsync pulse and beginning of the color burst?
Are there any ADV7181D registers that adjust any timing requirements for the SDP core?”