I am currently testing the AD9548 in our new design and have some questions.
The current configuration is:
- 1pps on Ref A.
- 1GHz Sysclk.
- 240MHz DPLL frequency.
- R divider 1.
- Output frequency 1Hz.
- I am currently using the evaluation board and software to control the PLL in my design.
Every time the PLL achieves phase lock, the output divider is synchronised which interrupts frequency generation as the divider network is held in reset for at least 1s. This is ok for the first time after power-up but should not be every time the PLL recovers from a hold-over condition. Better would be a smooth adjustment of the phase until it is aligned. How can that be achieved?
I noticed a few times after the PLL is reinitialised after a soft-reset that the tuning word is frozen and seems not to change for a long time. (I have set the averaging period to 100s in full increments). However, even after waiting for more than 100s there seems to be no change. This happens quite frequently. The only way I can recover from this appears to be to set the slew rate limit to 1000ns/s. What is the correct way to make the PLL start-up reliable without hanging?
Because of the very low loop bandwidth, it takes ages to achieve frequency and phase lock. Better would be to use a profile with a high loop bandwidth to achieve a quick lock and afterwards change to the "final" profile with a low bandwidth to get a stable output frequency. However, if I try this the PLL looses lock and re-synchronises again with the new profile. How can that be done in the correct way so the PLL stays locked while switching profiles?