we are designing and system with AD7626 operating at 10MHz where our customer expects all datasheet advertized parameters to be achieved. We are very worried about the CNSVT jitter, all ADI evaluation boards and refernce designs seem to use FPGA for CNST generation, but FPGA output has always a lot of jitter. As example Altera datasheet for the FPGA on AD7626 says PLL jitter could be of 300ps. With other FPGA vendor clock jitter estimates the best achievable jitter from FPGA output would be in 70ps RMS range, but could be as much as 400 ps p-p. We have verified that such jitter is present, and there is virtually no way to avoid it when using FPGA as CNVST source.
So the big question is how is the CNVST meant to be generated? It is not possible to use low jitter PLL with 10MHz as that would violate CNVST timings. When using low jitter clock, and FPGA clocked directly from this clock to derive CNVST timing (without using FPGA PLL) we would still expect 30ps jitter at least.
Is that acceptable? What is the recommended way?