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BF527 PPI RX mode

Question asked by crocodile on Nov 8, 2013
Latest reply on Nov 11, 2013 by CraigG

Hello Friends!

 

I work with PPI port on BF527-0.2 processor under uCLinux.

Design of processor's part of my board is based on bf527-ezkit and I used appropriate linux configuration file.

 

I'm going to use PPI for receiving 1D data with 1 external FS signals and external CLOCK.

This is my configuration routine:

    ioctl(fd,CMD_PPI_XFR_TYPE, CFG_PPI_XFR_TYPE_NON646);

    ioctl(fd,CMD_PPI_PORT_CFG, CFG_PPI_PORT_CFG_XSYNC1);

    ioctl(fd,CMD_PPI_FIELD_SELECT, CFG_PPI_FIELD_SELECT_XT);

    ioctl(fd, CMD_PPI_PACKING, CFG_PPI_PACK_DISABLE);

    ioctl(fd, CMD_PPI_SKIPPING, CFG_PPI_SKIP_DISABLE);

//    ioctl(fd, CMD_PPI_SKIP_ODDEVEN, CFG_PPI_SKIP_ODD);

    ioctl(fd, CMD_PPI_DATALEN, CFG_PPI_DATALEN_16);

    ioctl(fd, CMD_PPI_CLK_EDGE, CFG_PPI_CLK_EDGE_FALL);

    ioctl(fd, CMD_PPI_TRIG_EDGE, CFG_PPI_TRIG_EDGE_RISE);

    ioctl(fd, CMD_PPI_LINELEN, 159);

    ioctl(fd, CMD_PPI_SET_DIMS, CFG_PPI_DIMS_1D);

    ioctl(fd, CMD_PPI_DELAY, 0);

    ioctl(fd, CMD_PPI_GEN_FS12_TIMING_ON_WRITE, 0);

 

 

I can see frame, clock and data signals by oscilloscope.

 

And after this configuration I see high level on frame(FS1) pins of the proceesor.

When data source(fpga) starts to transfer data, processor still keep frame pin in the high state and can't take signals fronts, that source sent.

We can conclude that processor frame line is configured as output, but I point in the configuration routine that frame line should be input. (CFG_PPI_PORT_CFG_XSYNC1 , CFG_PPI_FIELD_SELECT_XT)

 

I checked control register state and it is in true value.

The frame(FS1) pin is in PORTJ and hasn't MUX and FER registers.

 

How I can use this pin like output?

Does Processor support this mode?

What registers should I check else?

 

Thanks and Regards,

Outcomes