I use the evalution board AD9914. I programming AD9914 in serial mode. I use a 100Mhz clock signal on connector J104 (“single ended clock in”). Jumper P105 (enable clock input) is set. With disabled PLL on connector J100 (SYNCLK) dds is generating correct clock signal 100/24=4.16Mhz. When I enable PLL and set “Feedback divider” to 25 – the VCO must set to 2500Mhz and SYNCLK then must be 2500/24=104.16Mhz. But SYNCLK is set to 108.2Mhz and PLL lock bit is SET! And if I off the external clock signal - then SYNCLK is still working and PLL lock bit is SET! Also I set bit “VCO cal enable” on time more then 20mS and then clear this bit. But this is not effect. What I do wrong?
Internal register setting:
P0_FTW: "064A9CDC"h; --DDS out=61.44Mhz VCO=2.5GHz