Is it possible to change the CLK polarity of the input clock from "latch at rising edge" to "latch at falling edge" in non DDR mode?
There is no bit to change the CLK polority of the input clock from "latch at rising edge" to "latch at falling edge" in non DDR mode of ADV7511.
However, the ADV7511 does have a "Clock Delay" register that can be used to change the timing between the rising edge of the input clock and the input data.
The setup time spec for the ADV7511 is 1nS minimum; If my data and clock edges occur at the same time I could use the clock delay setting to adjust the data sampling; I have tried this and see improvement in my 1600x1200 video when the delay is set to +1.6nS. So it seems that +1.6nS delay is delaying the data (or advancing the clock) - is this correct?
Hello. Can you create a new thread for your question so we can track it?
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