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The maximum PIPELINE DELAY of ADV7392.

Question asked by Tamu on Nov 6, 2013
Latest reply on Nov 13, 2013 by GuenterL



I have a question about PIPELINE DELAY of ADV7392.
There is a description about PIPELINE DELAY on datasheet P.10 as follows:
"AD Component Outputs (16×) SD oversampling enabled TYPICAL 84 Clock cycles"


Could you tell us the maximum clock cycles?
There is no description about the maximum.


The customer tries to implement video mute function from external chip during the maximum clock cycles
after register setting is completed in order not to see flicker in a moment for their automotive product.
So the customer wants to know maximum PIPELINE DELAY clock cycles.


Thank you.

Best regards.