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Forcing Alert (via SPI) corrupts SPI reads

Question asked by hight77 on Nov 5, 2013
Latest reply on Nov 6, 2013 by DragosB

I am seeing some strange behavior from the AD9361 when initializing.  I am following the No-OS initialization flow and the SPI interface seems to be getting messed up after writing to register 0x14 during the RX CP calibration.  I am trying to set up the AD9631 with a custom FPGA and I am using teraterm to write the SPI commands to the AD9361.

 

The script sets register 0x14 to 0x05 (the default value = 0x13), which disables ENSM pin control and forces the ENSM to the Alert state (per the cal manual, the AD9361 needs to be in the Alert state prior to CP cal).  When this occurs, reads from the registers are garbage.  The twist is that it happens every other time that I run the script!

 

I am checking for correct SPI reads after doing the aforementioned write.  Every other time that I run the script, subsequent reads are OK.  The next time, reads return garbage data.

 

I have inserted a 1 second delay after the write to register 0x14, in case there is some timing issue, but that didn't help.

 

I also wrote the value 0x01 to register 0x14 first, to disable ENSM pin control mode, but that didn't help either.  So it seems that forcing into Alert state is causing the AD9361 grief every other time.

 

Has anyone else experienced this phenomenon?

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