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AD7732 RDYFN and sampling rate issues

Question asked by manaloam on Nov 4, 2013
Latest reply on Nov 13, 2013 by JohnnyG



I have been using the AD7732 for a while now with a single channel enabled with no issues. Now I changed my code to use both channels and I ran into issues. In all of these cases I'm using continuous read mode.


First, when only one channel is enabled (either 0 or 1) everything works great: I wait for rdy to go low, assert 32 clock cycles to read the status register and the 24 bits of data and rdy goes high again. The status register RDY bit reads 1 reflecting the RDY bit in the ADC status register, appropriately.


When I enable both channels with identical settings as above and RDYFN is 0, then it works as above except the sampling rate is about halved. From the datasheet the sampling rate should not change much when changing the number of active channels. When reading the data, the channel status alternates between channel 0 and 1 as it should. However, the amount of time between two samples of the same channel doubles.


Finally, when RDYFN is 1 it skips one channel entirely. That is with RDYFN 1, I wait for the rdy line to go low and then assert 64 clock cycles to read the data for both channels. However, data for only one channel is read, except it's read twice; once for each 32 cycle set. And the status register now on the first read reads 1 for the rdy bit, while it reads 0 on the repeated read, which is consistent with reading data twice. I've tried delaying between the first and second 32 cycle assertion, but the same channel is still read twice.


Interestingly, when RDYFN is 1, then if I start the continuous conversion with channel 0 (by writing to the mode register using channel 0 when starting the continuous read mode), only channel 1 is read, while if I start with channel 1 only channel 0 is read.


Thanks in advance for any help!


Message was edited by: Moishe Einhorn It posted itself when I hit ctrl-s from habit.