I work with PPI port on BF527-0.2 processor under uCLinux.
I use buildroot version 2012R2-RC5 and toolchain version 2012R2-RC2.
Design of processor's part of my board is based on bf527-ezkit and I used appropriate linux configuration file.
By default in this configuration /dev/ppi0 module is used by frame buffer device and I were needed switch off this device in linux-menuconfig.
I'm going to use PPI for receiving 2D data with 2 external FS signals and external CLOCK.
This is my configuration routine:
ioctl(fd, CMD_PPI_PACKING, CFG_PPI_PACK_DISABLE);
ioctl(fd, CMD_PPI_SKIPPING, CFG_PPI_SKIP_DISABLE);
// ioctl(fd, CMD_PPI_SKIP_ODDEVEN, CFG_PPI_SKIP_ODD);
ioctl(fd, CMD_PPI_DATALEN, CFG_PPI_DATALEN_16);
ioctl(fd, CMD_PPI_CLK_EDGE, CFG_PPI_CLK_EDGE_FALL);
ioctl(fd, CMD_PPI_TRIG_EDGE, CFG_PPI_TRIG_EDGE_RISE);
ioctl(fd, CMD_PPI_LINELEN, 159);
ioctl(fd, CMD_PPI_NUMLINES, 120);
ioctl(fd, CMD_PPI_SET_DIMS, CFG_PPI_DIMS_2D);
ioctl(fd, CMD_PPI_DELAY, 0);// learn fpga
ioctl(fd, CMD_PPI_GEN_FS12_TIMING_ON_WRITE, 0);
after configuration I call read() and wait data.
I can see frame, clock and data signals by oscilloscope.
And after this configuration I see high level on frame pins of the proceesor.
When data source(fpga) starts to transfer data, processor still keep frame pins in the high state and can't take signals fronts, that source sent.
We can conclude that processor frame lines are configured as outputs, but I point in the configuration routine that frame lines should be inputs. (CFG_PPI_PORT_CFG_XSYNC23 , CFG_PPI_FIELD_SELECT_XT)
Please check me in my configuration and help me to resolve this issue.