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ZC702 & FMCOMMS2: error synthesizing design

Question asked by herwin on Oct 31, 2013
Latest reply on Nov 1, 2013 by jay_d

I'm trying to synthesize the PL for the ZC702/FMCOMMS2 (AD9361) reference design.  I have downloaded the latest release

and have followed the directions in

http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl

to generate the logic cores.

 

When trying to generate the netlist in XPS, I encountered the following error message.  I have tried this process with both ISE 14.4 and 14.6 but keep getting the same results.  What is this error message caused by?  Has anyone else encountered this before?


Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

ZynqConfig: Terminated for tcl mode

INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_0.

INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_1.

ERROR:EDK:2951 -

   Unknown Tcl procedure ::hw_axi_ad9361_v1_00_a::run_coregen called

ERROR:EDK - axi_ad9361_0 (axi_ad9361) - 

INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_2.

INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_3.

ERROR:EDK:440 - platgen failed with errors!

make: *** [implementation/system_processing_system7_0_wrapper.ngc] Error 2

Done!

 

Best regards

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