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Precision Clock Generator Frame Sync Inversion

Question asked by alemannia on Oct 29, 2013
Latest reply on Oct 29, 2013 by alemannia

Hi,

 

I am trying to configure the PCGs to provide clock and frame sync signals for different SPORT channels. Here is my setup so far:

 

MCLK (24.576 MHz)

    |

    |     PCG_A ( AUDIO )

    |    +------------------+   

    +--->| /4   = 6.144 MHz |--> CLK_A

    |    +------------------+        

    +--->| /256 = 96 kHZ    |--> FS_A

    |    +------------------+

    |

    |     PCG_B ( COM )

    |    +------------------+   

    +--->| /1  = 24.576 MHz |--> CLK_B

    |    +------------------+        

    +--->| /64 = 384 kHz    |--> FS_B

         +------------------+

 

Both PCGs are generating clock signals for left-justified SPORT transmission. In order for this to work the generated FS and CLK signals must be phase reversed. Meaning that a rising edge of FS happens on a falling edge of CKL. I have managed to achieve this on PCG A by adding a phase shift to the FS signal:

 

                            _   _  |_   _   _   _   _   _   _   _

  CLKIN (24.576 MHz)      _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_

                          _        |_______         _______

  CLK_A                    |_______|       |_______|       |___

                                   |_________________________________  

  FS_A (PHASE 0)          _________| 

                            _______|________________________

  FS_A (PHASE 2)          _|       |

                                   |

 

As the clock divider of PCG B is 1 I have no possibility to play with the phase shift between CLK/FS. It will always be the same.

 

                            _   _  |_   _   _   _   _   _   _   _

  CLKIN (24.576 MHz)      _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_

                            _   _  |_   _   _   _   _   _   _   _

  CLK_B                   _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_

                                   |_________________________________  

  FS_B (PHASE 0)          _________|                               

                                ___|_________________________________  

  FS_B (PHASE 1)       ________|                               


 

Is there another way of inverting the FS signal on PCG B?

 

I have tried:

> Change the functionality of FS and CLK by setting the CLK divider to 64 and the FS divider to 1 (bypass), then enabling the INVERTB bit, but the SRU won't let me connect PCG_FS_O to SPORT_CLK_I .

 

> Has a look into the MISC buffers which have the possibility of inverting signals but their outputs can only be used as pin enable inputs.

 

Any other ideas?

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