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How to configure SPORT CLK and FS internally?

Question asked by wangchongwisdom on Oct 28, 2013
Latest reply on Oct 29, 2013 by wangchongwisdom

I am trying to configure the Sharc DSP ADSP-21469_EZKIT SPORT 0 as the transmitter. The sample codes configure the CLK and FS signals externally generated. However, I need to generate the signal internally. I tried with the following code based on the sample code "AD1939_Block_Based_Talkthru_192kHz", but it is not working. The oscilloscope cannot see any period signal. I want to generated 6MHz CLK, 48kHz FS. Can someone help me?

 

initSRU.c

void initDAI(void)

{

    ...

    SRU(SPORT0_CLK_O, DAI_PB07_I);   /* DAIP7 (RSCLK1) to SPORT1 CLK (CLK) */

    SRU(HIGH, PBEN07_I);

 

    SRU(SPORT0_FS_O, DAI_PB08_I);    /* DAIP8 (RFS1) to SPORT1 FS (FS) */

    SRU(HIGH, PBEN08_I);

    ...

}

 

initSPORT01_TDM_mode.c

void initSPORT(void)

{

   ...

   *pDIV0 = 0x007F02A2; // 225M/4*6M-1 = 337, Since bit 0 in divisor register is reserved, the 16-bit value of DIV0 should be 337*2

              // 6M/48k-1 = 7F

   *pSPCTL0 = SCHEN_B | SDEN_B | SCHEN_A | SDEN_A | SPTRAN | SLEN32 | ICLK | IFS;

    ...

}

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