I downloaded the latest HDL 2.0 designs for the AD-FMCOMMS1-EBZ with ZC702, from the git repository, and followed the instructions outlined here to generate the *.ngc and *.v files.
I created a new PlanAhead 14.4 project, and imported the cf_xcomms_zc702 project, and updated the path to the IP core library, and created the top level HDL using PlanAhead.
However, when I try to synthesize the design, I get the following error:
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
ZynqConfig: Terminated for tcl mode
INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_0.
INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_1.
Unknown Tcl procedure ::hw_axi_ad9122_v1_00_a::run_coregen called
ERROR:EDK - axi_ad9122_0 (axi_ad9122) -
INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_3.
Unknown Tcl procedure ::hw_axi_ad9643_v1_00_a::run_coregen called
ERROR:EDK - axi_ad9643_0 (axi_ad9643) -
INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_4.
ERROR:EDK:440 - platgen failed with errors!
gmake: *** [implementation/system_processing_system7_0_wrapper.ngc] Error 2
Error while running "gmake -f system.make netlist".
ERROR: [Edk 24-166] (generate_target): Failed to execute XPS script. Please check for any errors reported by the XPS application in the console: [/project/xilinx-zc702-fmcomms1/hw/pa_proj/zc702-fmcomms1/zc702-fmcomms1.srcs/sources_1/edk/cf_xcomm_zc702/__xps/pa/_system_synth.tcl]