I'm wondering how I could best realize power saving during idle periods of the ADSP-21469 DSP.
- HOST interface on SPI
- Serial Flash on SPIB
- DDR2 memory
- Core timer counting seconds
- 8 SPORTS with I2S data (clocks from external)
- temperature sensor on TWI
Normally the chip runs with max. performance (450MHz CCLK, 225MHZ DDR2) which I need when data needs to be transfered from SPORT to FLASH and the other way. But there is plenty of time where the DSP has nothing to do.
I know about the IDLE instruction but the power calculation sheet indicates that I could save much more power when simply reducing CCLK.
How could I best achive a CCLK reduction by changing the PLL (without waiting on locking etc.)? Bypass PLL? Change PLLD?
The HOST issues an interrupt (IRQ2) before sending data over SPI, so that would be the place to switch back ot max. CCLK.
The data sheet states a minimum of 100MHz CCLK, so Bypass of the PLL -> CCLK = 12,288MHZ would be below that value.
What will happen to the peripherals (DDR2, DDR2 refresh, SPI, core timer,...).
Any other ideas to save power?
Thanks for any help!