I have 2 AD9467 FMC boards each attached to a Xilinx Virtex 6 based 3rd party PCIe card (vendor shall remain nameless because I don't recommend them). I have a Crystek 250 MHz oscillator for my clock that I'm splitting to both FMCs and I'm currently testing the analog input with a clean 10 MHz tone. Since I believe we want the default state, we first tried just plugging everything in (no board changes) and pulling off the data. I see the 10 MHz in the output, but I also see a whole bunch of spurs and 3 other strong tones that are definitely not at the input. I tried removing the external clock and still got data out, albeit a lot more noisy, leading me to believe it was still using the on-board clock. I added jumpers to pull PD low and set the external clock to OFF, but it had not impact.
Before I have our firmware guy add the SPI interface to the FPGA, I wanted to make sure we were doing everything else correctly. We are using the 250 MHz clock coming over the FMC for initial data handling, mostly to assure both FPGAs are synchronized (long story as to why that was the best way). And regarding the SPI interface, I was wondering if it was worthwhile to add a Microblaze and program it from there?
Any help would be appreciated.