bahrami.amin@yahoo.com

adv212 problem for mclk

Discussion created by bahrami.amin@yahoo.com on Dec 23, 2012
Latest reply on Oct 28, 2013 by bahrami.amin@yahoo.com
Branched from an earlier discussion

Dear Dave

I have a new problem with adv212

i connected mclk to the fpga directly and i set its frequency to 25 mhz .

pll_h--->0008

pll_l--->0084

 

every thing is ok and adv works correctly but some times it produces too many zeros to the final part of the code(zero padding after ffd9 is too much)

by the way, I changed mclk frequency to 74.25 and some times i saw different output which is not similar to input image any way

i think that problem occures because mclk is directly connected to fpga and for current limitations of fpga pins

can you help me plz?

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