When I check out the latest ADV7511 latest reference design for ZedBoard with git, the design can't be generated into bit files. When I check the design, I find that the two SPI is enabled and connect to EMIO and there is SPI interface IO constrains in ucf files, but there is no SPI logic in PL. The XPS will assert platgen.exe error when it generates the PS netlist files. When I disable the SPI in PS and remove the constrains in ucf files, the bit file can be generated, but it seems the bit file is not very fine and the display is flip screen. Anyone else meet the same issue?