AnsweredAssumed Answered

ADV7619 MCLK Frequency Setting

Question asked by snageli on Oct 17, 2013
Latest reply on Oct 18, 2013 by GuenterL

I would like to see if it is possible to have the MCLK output of the APx port be 24.756MHz so I can source other slave devices with this master clock when an HDMI connection is not present. I have tried the following:


  • I currently have a 24.756MHz crystal connected.
  • I have IO, address 0x04 set to 24.576MHz
  • I have IO, address 0x41 set to disable INT2
  • I have HDMI, address 0x13 set to coast under all conditions
  • I have tried different variants of DPLL, address 0xA08/0xB5.


I cannot seem to get a 24.756MHz clock frequency without an HDMI signal present for the DPLL to lock to.  That is the only condition in which I can get a 24.756MHz clock out of MCKL.  I am curious if this is possible.