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li1040 error for p0 on BF561

Question asked by jansen on Oct 16, 2013
Latest reply on Oct 17, 2013 by CraigG

I've inherited a BF561 project and added some new features to it. Now I'm getting Error li1040 as listed below.  I’ve found some forum posts that seem close to this issue, but not quite what I need. Or, I’m just not getting it.  I believe the external memory is getting mapped, at least in part, but I don’t believe it is being used to its fullest potential.  Ultimately, how can I free up more program memory for both cores?

 

If anyone could take a look and help me, I’d greatly appreciate it.  I've a list of questions at the bottom of this post.

 

Processor: BF561

External Flash Memory: 64Mbit (4Mx16) at address 0x20000000 configured for 16-bit data bus

External SDRAM: 2x 256Mbit (4Mx16x4banks) configured for 32-bit data bus.

VisualDSP++ version 4.5.3.0

 

Linker Error:

[Error li1040] "adsp-BF561_C.ldf":556 Out of memory in output section 'l1_code' in processor 'p0'

        Total of 0x178 word(s) were not mapped.

For more details, see 'linker_log.xml' in the output directory.

 

 

[Error li1040] "adsp-BF561_C.ldf":567 Out of memory in output section 'l1_code_cache' in processor 'p0'

        Total of 0x178 word(s) were not mapped.

For more details, see 'linker_log.xml' in the output directory.

 

From linker_log.xml:

[Error li1040] adsp-BF561_C.ldf:556 Out of memory in output section 'l1_code' in processor 'p0'

Total of 0x178 word(s) were not mapped.

0x178 words required for librt_fileio561y.dlb[meminit.doj](program):0x21a

[Error li1040] adsp-BF561_C.ldf:567 Out of memory in output section 'l1_code_cache' in processor 'p0'

Total of 0x178 word(s) were not mapped.

0x178 words required for librt_fileio561y.dlb[meminit.doj](program):0x21a

 

The lines/block pointed to in the ldf file:

        l1_code

        {

            INPUT_SECTION_ALIGN(4)

            __CORE = 0;

            INPUT_SECTIONS( $OBJECTS_CORE_A(L1_code) $LIBRARIES_CORE_A(L1_code))

            INPUT_SECTIONS( $OBJECTS_CORE_A(cplb) $LIBRARIES_CORE_A(cplb))

            INPUT_SECTIONS( $OBJECTS_CORE_A(cplb_code) $LIBRARIES_CORE_A(cplb_code))

            INPUT_SECTIONS( $OBJECTS_CORE_A(noncache_code) $LIBRARIES_CORE_A(noncache_code))

            INPUT_SECTIONS( $OBJECTS_CORE_A(program) $LIBRARIES_CORE_A(program))

        } >MEM_A_L1_CODE

 

        l1_code_cache

        {

            ___l1_code_cache = 0;

            INPUT_SECTION_ALIGN(4)

            INPUT_SECTIONS( $OBJECTS_CORE_A(L1_code) $LIBRARIES_CORE_A(L1_code))

            INPUT_SECTIONS( $OBJECTS_CORE_A(cplb) $LIBRARIES_CORE_A(cplb))

            INPUT_SECTIONS( $OBJECTS_CORE_A(cplb_code) $LIBRARIES_CORE_A(cplb_code))

            INPUT_SECTIONS( $OBJECTS_CORE_A(program) $LIBRARIES_CORE_A(program))

        } >MEM_A_L1_CODE_CACHE

 

From Memory Map xml:

Memory map of link project SHARED_MEMORY

Memory

Start address

End address

Qualifier

Width

Used words

Unused words

MEM_L2_SRAM

0xfeb00000

0xfeb1ffff

RAM

0x8

0xb724

0x148dc

MEM_ASYNC3

0x2c000000

0x2fffffff

RAM

0x8

0x4c

0x3ffffb4

MEM_ASYNC2

0x28000000

0x2bffffff

RAM

0x8

0x0

0x4000000

MEM_ASYNC1

0x24000000

0x27ffffff

RAM

0x8

0x0

0x4000000

MEM_ASYNC0

0x20000000

0x23ffffff

RAM

0x8

0x0

0x4000000

MEM_SDRAM0_BANK3

0x3000000

0x3ffffff

RAM

0x8

0x2a34c

0xfd5cb4

MEM_SDRAM0_BANK2

0x2000000

0x2ffffff

RAM

0x8

0xdbf24

0xf240dc

MEM_SDRAM0_BANK1

0x1000000

0x1ffffff

RAM

0x8

0xdbf24

0xf240dc

MEM_SDRAM0_HEAP

0x4

0xffffff

RAM

0x8

0x0

0xfffffc

 

Memory map of link project p0

Memory

Start address

End address

Qualifier

Width

Used words

Unused words

MEM_L2_SRAM

0xfeb00000

0xfeb1ffff

RAM

0x8

0x0

0x20000

MEM_ASYNC3

0x2c000000

0x2fffffff

RAM

0x8

0x0

0x4000000

MEM_ASYNC2

0x28000000

0x2bffffff

RAM

0x8

0x0

0x4000000

MEM_ASYNC1

0x24000000

0x27ffffff

RAM

0x8

0x0

0x4000000

MEM_ASYNC0

0x20000000

0x23ffffff

RAM

0x8

0x0

0x4000000

MEM_SDRAM0_BANK3

0x3000000

0x3ffffff

RAM

0x8

0x0

0x1000000

MEM_SDRAM0_BANK2

0x2000000

0x2ffffff

RAM

0x8

0x0

0x1000000

MEM_SDRAM0_BANK1

0x1000000

0x1ffffff

RAM

0x8

0x0

0x1000000

MEM_SDRAM0_HEAP

0x4

0xffffff

RAM

0x8

0x0

0xfffffc

MEM_A_L1_SCRATCH

0xffb00000

0xffb00fff

RAM

0x8

0x4c

0xfb4

MEM_A_L1_CODE_CACHE

0xffa10000

0xffa13fff

RAM

0x8

0x3ffa

0x6

MEM_A_L1_CODE

0xffa00000

0xffa03fff

RAM

0x8

0x4000

0x0

MEM_A_L1_DATA_B_CACHE

0xff904000

0xff907fff

RAM

0x8

0x0

0x4000

MEM_A_L1_DATA_B

0xff901000

0xff903fff

RAM

0x8

0x4c

0x2fb4

MEM_A_L1_STACK

0xff900000

0xff900fff

RAM

0x8

0x0

0x1000

MEM_A_L1_DATA_A_CACHE

0xff804000

0xff807fff

RAM

0x8

0x0

0x4000

MEM_A_L1_DATA_A

0xff800000

0xff803fff

RAM

0x8

0x202c

0x1fd4

 

Memory map of link project p1

Memory

Start address

End address

Qualifier

Width

Used words

Unused words

MEM_L2_SRAM

0xfeb00000

0xfeb1ffff

RAM

0x8

0x0

0x20000

MEM_ASYNC3

0x2c000000

0x2fffffff

RAM

0x8

0x0

0x4000000

MEM_ASYNC2

0x28000000

0x2bffffff

RAM

0x8

0x0

0x4000000

MEM_ASYNC1

0x24000000

0x27ffffff

RAM

0x8

0x0

0x4000000

MEM_ASYNC0

0x20000000

0x23ffffff

RAM

0x8

0x0

0x4000000

MEM_SDRAM0_BANK3

0x3000000

0x3ffffff

RAM

0x8

0x0

0x1000000

MEM_SDRAM0_BANK2

0x2000000

0x2ffffff

RAM

0x8

0x0

0x1000000

MEM_SDRAM0_BANK1

0x1000000

0x1ffffff

RAM

0x8

0x0

0x1000000

MEM_SDRAM0_HEAP

0x4

0xffffff

RAM

0x8

0x0

0xfffffc

MEM_B_L1_SCRATCH

0xff700000

0xff700fff

RAM

0x8

0x4c

0xfb4

MEM_B_L1_CODE_CACHE

0xff610000

0xff613fff

RAM

0x8

0x0

0x4000

MEM_B_L1_CODE

0xff600000

0xff603fff

RAM

0x8

0x2bca

0x1436

MEM_B_L1_DATA_B_CACHE

0xff504000

0xff507fff

RAM

0x8

0x0

0x4000

MEM_B_L1_DATA_B

0xff501000

0xff503fff

RAM

0x8

0x4c

0x2fb4

MEM_B_L1_STACK

0xff500000

0xff500fff

RAM

0x8

0x0

0x1000

MEM_B_L1_DATA_A_CACHE

0xff404000

0xff407fff

RAM

0x8

0x0

0x4000

MEM_B_L1_DATA_A

0xff400000

0xff403fff

RAM

0x8

0x11d8

0x2e28

 

Questions:

  1. How do I open up more program memory for both cores?
    • Last week I had the same issues on p1, but changed the code a little (moved stuff to p0) and that worked for a while.
  2. How will this affect processing speed?
  3. Does the WIDTH(8) macros cause me to ignore the upper bytes of most of this memory? Or does the BF do 8-bit accesses even though the hardware uses 16 and 32-bit data busses.
  4. Is ALL of the memory available being mapped and accessible?

 

Thank you!

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