We have implemented an RF board with AD9361 (rev 2), and a digital board based on an FPGA which is attached to it..
Our configuration is:
- SPI (default 24 bit mode)
- single port of data using DDR timing
- 2T2R data transfer in TDD mode
- Enable pin to control the ENSM
- Rx frame in pulse mode
- Ref-Clk into XTalN of 20MHz.
- Sampling rate 5.6MHz, BW 5MHz (just as an example).
We have been trying to operate an example from the AD9361 Evaluation SW ver 2.1.1 (The example works fine on an AD9361 evaluation board).
On our board it seems that the Tx power transmitted is very low (~-60dBm) – and we are sure we transmit the data correctly to the chip (we have checked it with many patterns – and it seems they are transmitted OK – but with very low power).
Furthermore we notice that the registers which should be updated after calibration (for example 0x8E-0x95) are with very low values – as if in the calibration process there was also problem with the Tx path.
We have tried several configuration (single path transmission, different powers, different data input, different frequencies, different channels, different RF clock ratios) on all of them the result is the same – very low power output.
I attach the register readout during Tx mode, and the project used to output the register init (we have adjusted to GPO to output our own sequence – but besides that we did not modify the registers init from the AD9361 evaluation SW).
I would appreciate any help.